Field of the Invention
The present invention relates to a discharge circuit, an information processing apparatus, a discharge method, and a storage medium.
Description of the Related Art
Conventionally, a stabilization circuit that stabilizes a power source voltage by connecting a capacitor between a power source and ground is widely known. For example, a circuit, which stabilizes a power source voltage by connecting a smoothing capacitor between a power source and ground at a final stage of an AC-DC power source circuit or a DC-DC power source circuit to make a non-DC component of the power source voltage flow to the ground, is known.
Further, for example, there is a known circuit which stabilizes a power source voltage by connecting a decoupling (bypass) capacitor between a power source of a connector and ground, and reducing a characteristic impedance of a power source line thereof to absorb fluctuations of a power source voltage due to disturbance noises.
Furthermore, for example, there is also a known circuit which stabilizes a power source voltage by arranging a decoupling capacitor near a semiconductor element, of which current consumption fluctuates, such as a transistor or a semiconductor element, to supply current upon fluctuations of the current consumption and to absorb switching noises of the semiconductor element.
In addition, Japanese Patent Application Laid-Open No. 8-205398 discusses a configuration in which a large-capacitance capacitor is connected between a power source and ground so that the capacitor supplies current in place of a power source upon instantaneous interruption of the power source. Japanese Patent Application Laid-Open No. 8-205398 discusses a discharge circuit in which a switching element and a resistor are connected in series, the discharge circuit being in parallel with the capacitor connected between the power source and ground. According to Japanese Patent Application Laid-Open No. 8-205398, when power is supplied, the switching element is turned off and the capacitor is charged. When the capacitor unit is removed, the switching element is turned on and charges stored in the capacitor are discharged to ground via the switching element and the resistor.
In the case where the configuration of Japanese Patent Application Laid-Open No. 8-205398 is applied to a device, such as a multifunction peripheral (MFP), from which the capacitor unit cannot be removed, it is desirable that the discharge circuit is subjected to OFF/ON control in conjunction with the ON/OFF control of the power source circuit. Further, though Japanese Patent Application Laid-Open No. 8-205398 discusses a configuration in which one discharge circuit is provided, it is desirable, in a device including a plurality of circuits, that discharge circuits are connected to power sources of the circuits, respectively. For example, conventionally, such a configuration that a plurality of power sources such as a core power source and an IO power source are input to one semiconductor element has been known.
In recent years, as semiconductor processes have been more finely divided, timing conditions for power supply and cutoff to a semiconductor element have become stricter. In addition, as MFPs have become highly functional, circuits have been complicated and timing conditions for power supply and cutoff among circuits have become stricter. Therefore, power cutoff timing control of each power source is important.
However, the above-described prior art technique has a following problem: when a power source voltage or current supplying ability with respect to circuits installed in a power source device for controlling discharge circuits or with respect to the discharge circuits decreases, the discharge circuits do not operate.
FIG. 6 is a timing chart illustrating conventional power cutoff timings.
In FIG. 6, a horizontal axis indicates time, and a vertical axis indicates voltage. A power source line 2000 indicates a waveform of a power source voltage discharged by a discharge circuit. A power source line 2001 indicates a waveform of a power source voltage for a circuit that performs ON/OFF control with respect to the discharge circuit. For convenience of explanation, the following refers to a case of a MFP as an example, as described below, assuming that the power source line 2001 indicates a power source that supplies power in a low power mode with a smaller power consumption than usually. A power source line 2002 indicates a state of the discharge circuit.
[Before Time 2010]
The power source line 2000 and the power source line 2001 are in a steady state in which power is continuously supplied. Respective capacitors connected between the power source line 2000 and ground, and between the power source line 2001 and ground have already been charged.
[From Time 2010 to Time 2011]
Upon the start of power source cutoff at time 2010, regarding the power source line 2000, the capacitor that will be described below is discharged by the discharge circuit, and the voltage starts decreasing. Regarding the power source line 2001, the capacitor that will be described below is discharged by current consumption by a load (such as a semiconductor element) that will be described below, and the voltage starts decreasing.
[After Time 2011]
All of AC-DC power sources that are to be described below are continuously cut off. The voltage of the power source for the circuit for controlling the discharge circuit decreases, and the discharge circuit does not operate. When the voltage of the power source line 2001 decreases, the discharge circuit becomes unable to operate, as indicated by 2002.
In the case where a large-capacitance capacitor is connected to the power source line 2000, the decrease of the voltage of the power source line 2000 takes time. For example, for power source stability, a large-capacitance capacitor is connected to a power source that is connected to a mechanism consuming much current such as a heater, a motor, a laser, etc. of an MFP, or a semiconductor element in which current consumption largely fluctuates, such as an image processing circuit. In this case, since power is not supplied to the mechanism consuming much current or the semiconductor element when the power source is cut off, the discharge of the large-capacitance capacitor takes much time.
The following describes details of a state in which the discharge circuit becomes unable to operate (after the time 2011).
For example, in the case where the switching element of Japanese Patent Application Laid-Open No. 8-205398 is formed with a field effect transistor (FET), when a gate voltage Vgs of the FET becomes below a threshold value Vth, drain current stops flowing, and the discharge circuit does not operate. In other words, this disables the power cutoff timing control by a plurality of discharge circuits.
If charges in a capacitor between a power source and ground are not discharged sufficiently, the voltage of the power source does not decrease sufficiently upon the power source cutoff. If the power source is turned on again before the voltage of the power source decreases sufficiently, transition occurs from the middle of power cutoff timing to the middle of the power supply timing. Accordingly, a power-on reset circuit does not operate, which causes the circuit to malfunction.
Further, upon power source cutoff, a signal is input to a circuit to which power is not supplied from a circuit to which power is supplied, power is supplied in a pseudo manner via a parasitic element from a signal line, and a semiconductor element deteriorates. In some cases, the worst happens such as breakdown of a semiconductor element caused by overcurrent that is significantly beyond drive capability of the semiconductor element, or by latchup.